Tag: clock

Adds selectable CPU and peripheral clock rates plus supervised power-on reset.

Current kits include a 7.3728 MHz single-speed version and a multispeed version. A DS1233 reset monitor holds the CPU in reset while power stabilizes and a button provides manual reset. The optional manual clock switch is not supplied.

Adds battery-backed date and time without consuming an Apple II expansion slot.

The ReActiveMicro version was in stock and backorderable on 2026-07-24; the Manila Gear version exposed selectable configurations and an Add to cart path. Neither design fits an Apple IIc or IIc Plus when a RAM card occupies the necessary space.

Replaces the 74LS08 clock logic in Atari XL and XE computers with four separately buffered O2 outputs.

The product exposed a login-or-register-to-buy path on 2026-07-27. Installation replaces a 74LS08; a non-socketed chip must be desoldered and the required 14-pin socket is not supplied. The installer must identify the motherboard's actual CPU O2 connection by continuity rather than relying blindly on a model example. Three outputs carry 680 pF capacitors, while the uncapped top output is intended for Ultimate 1MB; remove a corresponding capacitor if a capped output causes instability.

Replaces Apple II system ROMs with in-system programmable banks selected from an on-screen menu.

All four current model pages offered an order path on 2026-07-24. Optional video and MAP ROM functions require the matching socketed ICs and cables; many compact Apple II systems have those chips soldered.

Provides a modular Z80 processor with flexible clock and reset options.

The project provides a schematic, Gerbers, PCB design files, and kit or bare-PCB suppliers; an assembled version is not offered. PCB v1.0.0 needs a wire link across C7 when X2 is not populated. Enable only one voltage supervisor in a system.

Generates three independently selected clock outputs for RCBus processor and peripheral timing.

The project provides a schematic, Gerbers, PCB design files, and kit or bare-PCB suppliers; an assembled version is not offered. Check every destination jumper to avoid driving a bus clock signal from more than one source.

Adds two independently writable pulse-width modulation outputs.

The project supplies a schematic, Gerbers, PCB design files, and kit or bare-PCB paths. The base address must be even; 0x04 is the documented example. Pulse frequency is the selected clock divided by 128.

Adds two Zilog SIO/2 serial ports for terminals, printers, and other devices.

Current kits are offered for Standard or Enhanced Bus. The Standard version includes a 20-pin header exposing CLK2, TX2, and RX2. Jumpers can allow either FTDI connection to power the RC2014.

Adds a 5 V TTL serial port and an independently usable 7.3728 MHz clock.

The current product is a through-hole kit, with a bare PCB also listed elsewhere. It normally replaces an existing 68B50 or SIO/2 module; using it alongside another serial port requires backplane modifications.