Tag: fast ram

Adds 8 MB of Fast RAM and a bootable 44-pin IDE controller at the Amiga 500 CPU socket.

The assembled Lotharek revision exposed a login-or-register-to-buy path on 2026-07-27; the original Oleg Mishin design files, ROM, firmware, software, and four-layer PCB are public. The box contains only the board. Kickstart and Workbench 1.3 or newer can autoboot without a patched scsi.device. A socketed CPU makes installation simple, but an unsocketed CPU must be desoldered. Pin 1 must be observed when attaching CF or SD hardware because a reversed adapter can destroy the CPLD. The open repository documents the original A500 design, while the current seller alone claims A500 Plus support for its revised hardware.

Accelerates an Amiga 600 with a 68EC020, 68882 FPU, 9.5 MB of Fast RAM, MapROM, and IDE speedup.

Active- and passive-cooled versions both exposed order paths on 2026-07-27. The current Revision 3 uses two memory chips and original unused Motorola and DRAM parts whose exact types may vary. The seller strongly recommends recapping the A600 and using a fast CF or SD-to-IDE path; old ROM and Workbench combinations, old WHDLoad releases, and some games with the FPU enabled can fail. Firmware 14.3 is offered in 2K and 4K forms, and the page warns that choosing the wrong image is dangerous, so confirm the board version with the seller before JTAG programming.

Replaces a socketed 6502 with a W65816 running at up to 10 MHz, backed by fast RAM and programmable flash ROM.

The project publishes Eagle board and schematic files, VHDL and CPLD binaries, test software, and GPLv2-licensed documentation, but no current assembled seller was verified. Revision 1.2b is marked 'ok'; older revisions are prototypes. Building it depends on older Xilinx ISE-era tooling or a compatible programming path, two programmed flash devices, and a socketed host CPU. The author's 10 MHz timing uses 55 ns SRAM outside its rated access time; his burn-in test passed, but builders should not treat that result as a component guarantee.